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Single MOS Complementary Nanowire Circuits

Fig. 1:  Reconfigurable NAND/ NOR circuit a) realization of NAND and NOR functionality within a single nanowire. b)  Circuit of a cell including inverter as select element.

The multiple operation states of reconfigurable FETs open new opportunities for logic circuit design. Two interesting circuit strategies that were previously not accessible with conventional FETs are currently being studied. In the first one, layout generation and mapping of circuits is reduced to a single type of universal device of a sole material composition and size. This is distinctly different to state-of-the-art CMOS, where designs cope with different compositions, sizes, shared implantation wells and local isolations between different wells. In the second strategy, new types of circuits can be studied, that can have multiple functionalities as programmed on the fly through the individual select signals. Both circuit perspectives are enabled by the true symmetric IV behavior achieved in our RFET devices.

Fig. 2: IMixed-mode simulations: proof of functionality of NAND NOR circuit shown in Fig. 1 demonstrating reconfiguration at runtime. The cell always delivers full swing output.

Due to the reconfigurability of our RFET devices, our single MOS approach deliver an increased value per building block. One basis is given by the compact six transistor NAND/NOR cell (Fig. 1). Distinctly, this cell always operates in a complementary manner, reaching a full swing output and exhibiting the same delay for both functions (Fig. 2). The other basis is the integration of multiple gate electrodes along the nanowire channel, lumping various series transistors within a single one showing the same on-resistance as dual gated RFETs and sparing interconnects and area for isolations and wells.

Fig. 3: Compact 3XOR cell composed of only eight transistors. This computing block is used for building compact fulladders.


We have shown a comprehensive  library of functionality enhanced logic gates. A prominent example is  given by a 1-bit adder which only employs 16 transistors vs. typical CMOS implementations with 28 transistors. In addition critical paths are significantly reduced leading to a reduction of the overall structural delay by approximately 50 % (e.g. Fig. 3). Proper radial scaling and the implementation of germanium channels can boost performance in terms of significantly lower dynamic power consumption and lower the intrinsic delay.


Contact: Dr. Walter M. Weber


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