Sie sind hier: Startseite / Forschung / Reconfigurable Devices / Charge Trapping Devices

Charge Trapping Devices

Dieser Text ist nur in Englisch verfügbar.
Fig. 1:  Band diagram during erase at -10 V. Hole injection from the Si-channel and electron injection from the gate are indicated. The trap distribution (DT) in the dielectric is shown.

The economical scaling of conventional planar floating gate FLASH devices is expected to end at the 16nm technology node. Tiny devices simply run out of electrons for reliable information storage. In order to follow Moore’s law of increasing the integration density at minimal fabrication costs, novel 3D integration concepts are under development, which predominantly rely on charge trapping effects. Besides that, charge trapping devices are widely used as embedded non-volatile memory (NVM) due to their comparatively convenient integration into CMOS technologies. Hence, the modeling, understanding and optimization of charge trapping transistors gain increasing attention.


Fig. 2: Schematic diagram of the on-chip circuit to collect the current through the SONOS transistor S gate dielectric during the erase pulse.

In our work we developed an improved  model for charge injection via inelastic tunneling in multilayer gate stacks. The model allows the extraction of the trap distribution in the band gap of silicon nitride based non-volatile memories from program and discharge transients (Fig. 1). Based on the model we assessed the minimum voltage scaling potential of SONOS non-volatile memory transistors for the application in NV-SRAM cells. By properly scaling the dielectric films and utilizing electrical simulation we have determined the limit to be around 8V in terms of operation voltage and 6-8 nm for the equivalent oxide thicknesses. For scaled devices the reliability deteriorates significantly and all layer thicknesses need to be carefully optimized to reach acceptable reliability characteristics. Finally, together with our project partners we have demonstrated successful scaling of SONOS transistor with an operating voltage of about 8 V and 2x105 endurance cycles.

Fig. 3: Correlation between accumulated electron charge density from the gate during cycling and VTH shift of the erased state after 104 s.


The reliability degradation was analyzed in detail. Especially electrons injected from the gate are supposed to be responsible for the degradation. An on-chip test circuit was developed to measure those gate currents during program and erase operation (Fig. 2). A clear correlation was found with retention-after-cycling experiments and interface degradation measured with the pulsed-capacitance technique. Based on the results, defect generation in the tunnel oxide was identified as the main degradation mechanism (Fig. 3). The outcome is supported by electrical simulations of the transient behavior of the SONOS gate dielectric during program and erase.


Contact: Dr. Stefan Slesazeck


NaMLab gGmbH
Nöthnitzer Str. 64 a
01187 Dresden

Tel. +49.351.21.24.990-00
Fax. +49.351.475.83.900




Wappen des Freistaates Sachsen

Diese Maßnahme wird mitfinanziert durch Steuermittel auf der Grundlage des vom Sächsischen Landtag beschlossenen Haushaltes.

More information

NaMLab – a TU Dresden company

Logo TU Dresden


Member/Partner of