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Device Reliability

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Fig. 1
Fig. 1: Voltage transients of floating MIM stack capacitor after applying positive and negative stress voltage for 100 seconds.

Scaling of microelectronic devices is tightly linked to the availability of mature and reliable integration of new materials. Those materials applied on a nanometer scale act as gate insulator, high conductivity metals, stress or strain layers or memory dielectrics. NaMLab performs electrical stress measurements on a large variety of devices to assess the reliability of the used dielectric materials. Fig. 1 depicts the results of the dielectric absorption characterization of capacitor structures to determine the discharging dynamics of defects in metal-insulator-metal stacks. The de-trapping dynamic has strong influence on the time dependent dielectric breakdown (TDDB) behavior. If defects are discharged during relaxation between two AC stress cycles the wear out of the material is increased due to overall larger current flow. In contrast, if traps stay charged, that effect is irrelevant and the AC stress case leads to a lower effective stress compared to DC case.

Fig. 2
Fig. 2: Change in effective overlap capacitances from gate to source CGS (blue) and to drain CGD (red) after DC stressed with respect to VGS and VDS. Extracted from S-parameter at frequency of 20 GHz.  




In face of the increasing complexity of power devices or high performance logic devices any compromise in reliability is not acceptable. Especially for high dielectric constant gate insulators, the fundamental understanding of bias temperature instability (BTI), hot carrier injection (HCI), stress induced leakage currents (SILC), and TDDB are of major interest. Single trap spectroscopy methods as time dependent defect spectroscopy (TDDS) or random telegraph noise (RTN) measurements give deeper inside into the materials electronic structure. Besides the degradation of DC-parameter such as threshold voltage VTH or saturation current IDsat the correct understanding of degradation mechanisms for RF-parameters becomes increasingly important. Fig. 2 depicts the change in effective overlap capacitances from gate to drain CGD and source CGS in 22 nm FD-SOI devices after DC stress as extracted from S-parameter measurements on single transistors at 20 GHz.


Fig. 3
Fig. 3: Change in operation frequency of a ring-oscillator in dependency on the stress time. An optimized measurement setup with increased frequency resolution gives deeper insight into the physical degradation mechanisms.


To further deepen the understanding of use-case realistic stress conditions we put additional focus on the assessment of circuit reliability. Under circuit realistic stress conditions the parameter shift is small and attention has to be paid on the measurement resolution for correct degradation prediction over whole device lifetime. In Fig. 3 results of an optimized frequency shift measurement of a ring oscillator are depicted. The high measurement resolution allows a precise determination of the time slope of degradation that is important for the determination of the underlying physical mechanism.



Contact: Dr. Stefan Slesazeck


NaMLab gGmbH
Nöthnitzer Str. 64 a
01187 Dresden

Tel. +49.351.21.24.990-00
Fax. +49.351.475.83.900




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